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1 datasheet digital dual output, 7-phase configurable pwm controller with adaptive voltage scaling (avsbus) bus isl68137 the isl68137 is a digital dual output, flexible multiphase (x+y 7) pwm controller with avsbus (adaptive voltage scaling interface). the isl68137 can be configured to support any desired phase assignments up to a maximum of 7 phases across the 2 outputs (x+y). for example, 6+1, 5+2, 4+2, 3+3, 3+2, or even a single output operation as a 7+0 configuration are supported. the flexible phase arrangement, combined with pmbus and avsbus interfaces, allows the device to support any demanding power supply requirement. the isl68137 with avsbus complements pmbus by providing a common interface that accelerates point-to-point communication between the controller and th e load to statically and dynamically control the processor voltage, thus delivering a balanced and power efficient solution. avsbus can be used exclusively once the device is configured via pmbus. the isl68137 utilizes intersil?s proprietary linear synthetic digital current modulation scheme to achieve the industry?s best combination of transient respon se and ease of tuning while addressing the challenges of modern multiphase designs. device configuration and telemetry monitoring is accomplished using intersil's intuitive powernavigator? gui. the isl68137 device supports on-chip nonvolatile memory to store various configuration setting s that are user selectable via pin-strap, giving system designers increased power density to configure and deploy multiple configurations. the device supports an automatic phase add/drop feature to allow maximum efficiency across all load ranges. thresholds for automatic phase add/drop are user programmable using the powerful powernavigator? gui. the isl68137 supports a comp rehensive fault management system to enable the design of highly reliable systems. from a multitiered overcurrent protection scheme, to the configurable power-good and output over voltage/undervoltage fault thresholds and temperature moni toring, virtually any need is accommodated. with minimal external components, easy configuration, robust fault management and highly a ccurate regulation capability, implementing a high performance multiphase regulator has never been easier. applications ? networking equipment ? telecom/datacom equipment ? server/storage equipment ? point-of-load power supply (memory, dsp, asic, fpga) features ? pmbus 1.3 and avsbus compliant - telemetry - v in , v out , i out , power in/out, temperature and various fault status registers - individual avsbus interface enables high speed voltage changes ? advanced linear digital modulation scheme - zero latency synthetic current control for excellent hf current balance - dual edge modulation for fastest transient response ? auto phase add/drop for excellent load vs efficiency profile ? flexible phase configuration - 7+0, 6+1, 5+2, 4+3 phase operation - operation using less than 7 phases between 2 outputs is also supported ? diode braking for overshoot reduction ? differential remote voltage sensing supports 0.5% closed loop system accuracy over load, line and temperature ? highly accurate current sensing for excellent load line regulation and accurate ocp - supports isl99227 60a smart power stages - supports dcr sense with integrated temperature compensation ? supports phase doubler (isl6617a) for up to 14-phase operation ? comprehensive fault management enables high reliability systems - pulse-by-pulse phase current limiting - total output current protection - output and input ov/uv - open voltage sense detect - black box recording capability for faults ? intuitive configuration via powernavigator ? gui - nvm to store up to 8 configurations ? pb-free (rohs compliant) related literature ? for a full list of related documents, visit our website - isl68137 product page september 27, 2016 fn8757.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2016. all rights reserved intersil (and design) and powernavigator are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl68137 2 fn8757.0 september 27, 2016 submit document feedback table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 driver, drmos and smart power stage recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical application: 6+1 configuration with isl99227 sps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical application: 4+3 configuration with isl99227 sps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical application: 5+2 configuration with dcr sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical application: phase doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pwm modulation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pmbus address selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 phase configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 automatic phase add and drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output voltage configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 temperature sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 lossless input current and power sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 current feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 stored configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 fault monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-good signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output current protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 smart power stage oc fault detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 thermal monitoring and protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 layout and design considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pmbus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pmbus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 pmbus command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pmbus use guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pmbus data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pmbus command detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 adaptive voltage scaling (avsbus) functionality and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 avsbus master send subframe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 avsbus slave response subframe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 avsbus command detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
isl68137 3 fn8757.0 september 27, 2016 submit document feedback pin configuration isl68137 (48 ld qfn) top view ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # isl68137iraz isl68137 irz -40 to +85 48 ld 6x6 qfn l48.6x6b notes: 1. add ?-t? suffix for 4k unit or ?-t7a? suffix for 250 unit tape and reel options. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), please see product information page for isl68137 . for more information on msl please see techbrief tb363 . table 1. key differences between family of parts part number phase configuration output x/output y specification supported package isl68137 x+y 7 pmbus/avsbus qfn 48 ld, 6x6mm isl68134 x+y 4 pmbus/avsbus tqfn 40 ld, 5x5mm isl68127 x+y 7 pmbus qfn 48 ld, 6x6mm isl68124 x+y 4 pmbus tqfn 40 ld, 5x5mm 12 dnc dnc tmon1 1 2 3 4 5 6 7 8 9 10 36 35 34 33 32 31 13 14 15 16 17 18 19 20 40 39 38 37 tmon0 vccs vcc sa vsen0 rgnd0 csrtn1 en1 twarn cs2 csrtn2 cs3 cs4 csrtn4 pwm3 pwm2 en0 gnd 11 21 22 23 24 cs5 pg0 pg1 scl pwm1 pwm0 salrt avs_mda csrtn5 avs_clk pwm4 avs_sda sda vinsen csrtn3 cs1 config pwm5 30 29 28 27 26 25 41 42 43 44 45 46 47 48 dnc avs_vddio vsen1 rgnd1 dnc cs6 csrtn6 pwm6 cs0 csrtn0 (epad)
isl68137 4 fn8757.0 september 27, 2016 submit document feedback functional pin descriptions refer to table 4 on page 21 for design layout considerations. pin number pin name description 7, 6, 5, 4, 3, 2, 1 pwm[6:0] pulse width modulation outputs. conn ect these pins to the pwm input pins of 3.3v logic compatible in tersil smart power stages, driver ic(s) or power stages. 8 avs_clk avsbus clock input pin. connect to ground if not used. 9 avs_sda avsbus data output pin. leave open if not used. 10 avs_mda avsbus data input pin. connect to ground if not used. 11 avs_vddio avsbus reference voltage input pin. leave open if not used. 12, 46, 47, 48 dnc do not connect any signals to these pins. 13 en0 input pin used for enable control of output 0. active high. connect to ground if not used. 14 en1 input pin used for enable control of output 1. active high. connect to ground if not used. 15 twarn thermal warning flag. this open-drain output will be pulled low in the event of a sensed over-temperature at tmon pins without disabling the regulators. maximum pull-up voltage is v cc . 16 pg0 open-drain power-good indicators for output 0. maximum pull-up voltage is v cc . 17 pg1 open-drain power-good indicators for output 1. maximum pull-up voltage is v cc . 18 scl serial clock signal pin for smbus interface. maximum pull-up voltage is v cc . 19 sda serial data signal pin for smbus interface. maximum pull-up voltage is v cc . 20 salrt serial alert signal pin for smbus interface. maximum pull-up voltage is v cc . 21 config configuration id selection pin. see table 3 for more details. 22 vinsen input voltage sense pin. connect to vin through a resist or divider (typically 40.2k/10k) with a 10nf decoupling capacitor. 23 vsen1 positive differential voltage sense input for output 1. connect to positive remote sensing point. connect to ground if not used. 24 rgnd1 negative differential voltage sense input for output 1. connect to negative remote sensing point. connect to ground if not used. 25, 27, 29, 31, 33, 35, 37 csrtn[6:0] the cs and csrtn pins are current sense inputs to individual phase differential amplifiers. unused phases should have their respective current sense inputs grou nded. the isl68137 supports smart power stage, dcr and resistor sensing. connection details de pend on current sense method chosen. 26, 28, 30, 32, 34, 36, 38 cs[6:0] 39 rgnd0 negative differential voltage sense input for output 0. connect to negative remote sensing point. connect to ground if not used. 40 vsen0 positive differential voltage sense input for output 0. connect to positive remote sensing point. connect to ground if not used. 41 sa pmbus address selection pin. see table 2 on page 13 for more details. 42 vcc chip primary bias input. connect this pin directly to a +3.3v supply with a high quality mlcc bypass capacitor. 43 vccs internally generated 1.2v ldo logic supply from vcc. decouple with 4.7f or greater mlcc (x5r or better). 44 tmon0 input pin for external temperature measurement at ou tput 0. supports diode based temperature sensing as well as smart power stage sensing. refer to section ? temperature compensation ? on page 16 for more information. 45 tmon1 input pin for external temperature measurement at ou tput 1. supports diode based temperature sensing as well as smart power stage sensing. refer to section ? temperature compensation ? on page 16 for more information. epad gnd package pad serves as gnd return for all chip functi ons. connect directly to system gnd plane with multiple thermal vias.
isl68137 5 fn8757.0 september 27, 2016 submit document feedback driver, drmos and smart power stage recommendation intersil part number quiescent current (ma) gate drive voltage (v) number of drivers comments isl99227 4.85 5 single 60a, 5x5 smart power stage isl99140 0.19 5 single 40a, 6x6 drmos isl6596 0.19 5 single connect isl6596 vctrl to 3.3v isl6617a 5 n/a n/a phase doubler with 5v pwm output to be compatible with a 60a drmos or with 60a smart power stage. supp orts up to a 14-phase design. internal block diagram figure 1. internal block diagram isum-0 vsa adc vdroop pid isum-1 adc cycle- cycle ocp adc cycle- cycle ocp adc cycle- cycle ocp adc cycle- cycle ocp adc cycle- cycle ocp adc cycle- cycle ocp adc cycle- cycle ocp summed ocp current ac fb vsa adc vdroop pid current ac fb summed ocp adc fault and telemetry manager scl sda salrt pmbus interface status manager pg0 pg1 twarn cpu nvm ov uv + - + - ov uv + - + - loop manager en0 en1 pwm0 phase manager digital dual edge modulator digital dual edge modulator pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 vinsen tmon0 tmon1 vccs vcc ldo config sa blackbox vse n1 rgnd1 vse n0 rgnd0 cs6 csrtn6 cs5 csrtn6 cs4 csrtn4 cs3 csrtn3 cs2 csrtn2 cs1 csrtn1 cs0 csrtn0 avs_vddio avs_sda avs_mda avs_clk avsbus interface
isl68137 6 fn8757.0 september 27, 2016 submit document feedback typical application: 6+1 config uration with isl99227 sps figure 2. typical application: 6+1 configuration with isl99227 sps vcc vccs 4.7f tmon0 rgnd0 vsen0 salrt sda scl 4.7f pwm refin tmon fault# imon pvcc vcc boot phase sw gnd vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm0 csrtn0 cs0 pwm6 csrtn6 cs6 pwm1 csrtn1 cs1 pwm2 csrtn2 cs2 pwm3 csrtn3 cs3 pwm4 csrtn4 cs4 pwm5 csrtn5 cs5 470pf 470pf 470pf 470pf 470pf 470pf 470pf tmon1 rgnd1 vsen1 470pf 100 isl99227 c out vout0 vout1 c out isl99227 isl99227 isl99227 isl99227 isl99227 isl68137 pg0 en0 pg1 en1 1k 1k vinsen 0.01f 10k 40.2k twarn config sa 12v 3.3v gnd gnd gnd gnd gnd gnd avs_vddio avs_mda avs_sda avs_clk 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 470pf 100 100 100 100 100 100 100 isl99227
isl68137 7 fn8757.0 september 27, 2016 submit document feedback typical application: 4+3 config uration with isl99227 sps figure 3. typical application: 4+3 configuration with isl99227 sps vcc vccs 4.7f tmon0 rgnd0 vsen0 salrt sda scl 4.7f pwm refin tmon fault# imon pvcc vcc boot phase sw gnd vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v pwm0 csrtn0 cs0 pwm6 csrtn6 cs6 pwm1 csrtn1 cs1 pwm2 csrtn2 cs2 pwm3 csrtn3 cs3 pwm4 csrtn4 cs4 pwm5 csrtn5 cs5 470pf 470pf 470pf 470pf 470pf 470pf 470pf tmon1 rgnd1 vsen1 470pf 100 isl99227 c out vout0 vout1 c out isl99227 isl99227 isl99227 isl99227 isl99227 isl68137 pg0 en0 pg1 en1 1k 1k vinsen 0.01f 10k 40.2k twarn config sa 12v 3.3v gnd gnd gnd gnd gnd gnd avs_vddio avs_mda avs_sda avs_clk 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 470pf 100 100 100 100 100 100 100 isl99227
isl68137 8 fn8757.0 september 27, 2016 submit document feedback typical application: 5+2 conf iguration with dcr sensing figure 4. typical application: 5+2 configuration with dcr sensing vcc vccs tmon0 rgnd0 vsen0 salrt sda scl 4.7f pwm0 csrtn0 cs0 pwm6 csrtn6 cs6 pwm1 csrtn1 cs1 pwm2 csrtn2 cs2 pwm3 csrtn3 cs3 pwm4 csrtn4 cs4 pwm5 csrtn5 cs5 tmon1 rgnd1 vsen1 isl68137 pg0 en0 pg1 en1 1k 1k vinsen 0.01f 10k 40.2k twarn config sa 12v 3.3v pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd pwm en thdn pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v isl99140 gnd vout1 c out vout0 c out avs_mda avs_sda avs_clk avs_vddio
isl68137 9 fn8757.0 september 27, 2016 submit document feedback typical application: phase doubler figure 5. typical application: phase doubler pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v 100 vout1 c out gnd 0.1f lgctrl vcc vccs 4.7f tmon0 rgnd0 vsen0 salrt sda scl 4.7f pwm0 csrt0 cs0 pwm6 csrtn6 cs6 pwm1 csrtn1 cs1 pwm2 csrtn2 cs2 pwm3 csrtn3 cs3 pwm4 csrtn4 cs4 pwm5 csrtn5 cs5 470pf tmon1 rgnd1 vsen1 isl68137 pg0 en0 pg1 en1 1k vinsen 0.01f 10k 40.2k twarn config sa 12v 3.3v pwmin en_sync iout vcc csrtna isl6617a gnd 0.1f csena pwma csrtnb csenb pwmb 5v isl99226b/7b pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v 470pf gnd 0.1f lgctrl isl99226b/7b pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v gnd 0.1f lgctrl 470pf pwmin en_sync iout vcc csrtna isl6617a gnd 0.1f csena pwma csrtnb csenb pwmb 5v isl99226b/7b pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v gnd 0.1f lgctrl isl99226b/7b pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v gnd 0.1f lgctrl 470pf pwmin en_sync iout vcc csrtna isl6617a gnd 0.1f csena pwma csrtnb csenb pwmb 5v isl99226b/7b pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v gnd 0.1f lgctrl isl99226b/7b pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v gnd 0.1f lgctrl 470pf pwmin en_sync iout vcc csrtna isl6617a gnd 0.1f csena pwma csrtnb csenb pwmb 5v isl99226b/7b pwm refin tmon fault# imon pvcc vcc boot phase sw vin 0.1f 2x22f 12v 5v gnd 0.1f lgctrl isl99226b/7b avs_vddio avs_mda avs_sda avs_clk
isl68137 10 fn8757.0 september 27, 2016 submit document feedback absolute maximum rating s thermal information vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.3v vccs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.6v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . (gnd - 0.3v) to v cc + 0.3v esd rating: human body model (tested per js-001-2014) . . . . . . . . . . . . . . . . . . 2kv charged device model (tested per js-002-2014) . . . . . . . . . . . . . . . 1kv latch-up (tested per jesd-78d; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance ( notes 4 , 5 ) ? ja (c/w) ? jc (c/w) 48 ld 6x6 qfn package . . . . . . . . . . . . . . . 27 1 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3v 5% ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3.05v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, v cc = 3.3v, unless otherwise specified. boldface limits apply across the operating temperature range -40c to +85c. parameter test conditions min ( note 7 )typ max ( note 7 )unit v cc supply current nominal supply current v cc = 3.3vdc; en1/2 = v ih , f sw = 400khz 90.5 ma shutdown supply current v cc = 3.3vdc; en1/2 = 0v, no switching 11.4 ma vccs ldo supply output voltage 1.20 1.25 1.30 v maximum current capability excluding internal load 50 ma power-on reset and input voltage lockout v cc rising por threshold 2.7 2.9 v v cc falling por threshold 1.0 v enable (en0 and en1) input threshold 2.3 v enable (en0 and en1) low to high ramp delay (ton_delay) 200 s por to initialization complete time 30 40 ms output voltage characteristics ( note 6 ) output voltage adjustment range 0.25 3.05 v output voltage set-point accuracy set-point 0.8v to 3.05v -0.5 0.5 % set-point 0.25v to <0.8v -5 5 mv voltage sense amplifier open sense current only during open pin check of initialization 22 a input impedance (vsen - rgnd) 200 k maximum common-mode input v cc - 0.2 v maximum differential input (vsen - rgnd) 3.05 v current sense and overcurrent protection maximum common-mode input (sps mode) csrtnx - gnd 1.6 v maximum common-mode input (dcr mode) csrtnx - gnd 3.3 v current sense accuracy isen to adc accuracy -2 2 %
isl68137 11 fn8757.0 september 27, 2016 submit document feedback average overcurrent threshold resolution 0.1 a cycle-by-cycle current limiting threshold accuracy 0.1 a digital droop droop resolution 0.01 mv/a oscillators accuracy of switching frequency setting when set to 500khz 480 500 520 khz accuracy of switching frequency setting -4 4 % switching frequency range 0.2 1.0 mhz soft-start rate and voltage transition rate minimum soft-start ramp rate programmable minimum rate 20 s maximum soft-start ramp rate programmable maximum rate 10 ms soft-start ramp rate accuracy -4 4 % minimum transition rate programmable minimum rate 0.1 mv/s maximum transition rate programmable maximum rate 100 mv/s transition rate accuracy -4 4 % pwm output pwmx output high level i out = 4ma v cc - 0.4 v pwmx output low level i out = 4ma 0.4 v pwmx output tri-state i ol v oh = v cc 1 a pwmx output tri-state i oh v ol = 0v -1 a thermal monitoring and protection temperature sensor range -50 150 c temperature sensor accuracy tmon to adc accuracy -4.5 4.5 % twarn output low impedance 4 9 13 ? twarn hysteresis 3c power-good and protection monitors pg output low voltage i out = 8ma load 0.4 v pg leakage current with pull-up resistor externally connected to vcc 0.5 1.0 a overvoltage protection threshold resolution 1mv undervoltage protection threshold resolution 1mv overvoltage protection threshold when disabled v cc - 0.2 v input voltage sense input voltage accuracy vinsen to adc accuracy -2.5 2.5 % input voltage protection threshold resolution 1mv avsbus avsbus vddio input voltage range 0.90 3.63 v avsbus clk, mda, input high level 0.6 * v ddio v avsbus clk, mda, input low level 0.4 * v ddio v electrical specifications recommended operating conditions, v cc = 3.3v, unless otherwise specified. boldface limits apply across the operating temperature range -40c to +85c. (continued) parameter test conditions min ( note 7 )typ max ( note 7 )unit
isl68137 12 fn8757.0 september 27, 2016 submit document feedback avsbus sda, output high level 0.8 * v ddio v avsbus sda, output low level 0.2 * v ddio v avsbus clk maximum frequency 50 mhz avsbus clk minimum frequency 5 mhz smbus/pmbus salert, sda output low level i out = 4ma 0.4 v scl, sda input high/low threshold 1.25 v scl, sda input hysteresis 2mv scl maximum frequency 0.05 2.00 mhz notes: 6. these parts are designed and adjusted for accuracy with all errors in the voltage loop included. 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. electrical specifications recommended operating conditions, v cc = 3.3v, unless otherwise specified. boldface limits apply across the operating temperature range -40c to +85c. (continued) parameter test conditions min ( note 7 )typ max ( note 7 )unit typical performance curves figure 6. nominal supply current vs temperature figure 7. shutdown supply current vs temperature 0.050 0.055 0.060 0.065 0.070 0.075 0.080 0.085 0.090 0.095 0.100 -40-20 0 20406080100 ambient temperature ( o c) i cc (a) i cc (a) 0 0.01 0.02 0.03 0.04 0.05 -40-20 0 20406080100 ambient temperature ( o c)
isl68137 13 fn8757.0 september 27, 2016 submit document feedback functional description overview the isl68137 is a digital dual output 7-phase pwm controller that can be programmed for single output 7+0, dual output 6+1, 5+2, or 4+3 phase operation. op eration using less than 7 phases between 2 outputs is also supporte d. existing digital multiphase solutions utilize analog compar ator based schemes (nonlinear) to bolster the inadequate transient response common to many digital multiphase solutions. the isl68137 uses a linear voltage regulation scheme to address tran sient loads. as a result, it is much easier for users to configure and validate their designs when compared with nonlinear schemes. by combining a proprietary low noise and zero latency digital current sense scheme with cutting edge digital design techniques, intersil is able to meet transient demands without resorting to nonlinear schemes. in addition, the isl68137 can store up to 8 user configurations in nvm and allows the user to select the desired configuration via pin-strap (config). the result is a system that is easy to configure and deploy. a number of performance enhancing features are supported in the isl68137. these include avsbus control, diode braking, automatic phase dropping, dcr/resistor/smart power stage current sense support, load line regulation and multiple temperature sensing options. to facilitate configuration development, the powernavigator? gui provides a step-by-step arrangement for setup and parametric adjustment. once a configuration has been set, the user may employ powernavigator? to monitor telemetry or use a direct pmbus interface based on the supported command set. pwm modulation scheme the isl68137 uses intersil's proprietary linear synthetic current modulation scheme to improve transient performance. this is a unique constant frequency, dual edge pwm modulation scheme with both pwm leading and trailing edges being independently moved to give the best response to transient loads. current balance is an inherent part of the regulation scheme. the modulation scheme is capable of overlapping pulses should the load profile demand such operation. in addition, the modulator is capable of adding or removing pulses from a given cycle in response to regulation demands while still managing maximum average frequency to safe levels. for dc load conditions the operating frequency is constant. pmbus address selection when communicating with multiple pmbus devices on a single bus, each device must have its own unique address so the host can distinguish between the devices. the device address can be set using a 1% resistor on the sa pin according to the pin-strap options listed in table 2 . phase configuration the isl68137 supports up to two regulated outputs through seven configurable phases. either output is capable of controlling up to seven phases in any arbi trary mix. phase assignments are accomplished via the powernavigator? gui. while the device supports arbitrar y phase assignment, it is good practice to assign phases to output 1 in descending sequential numerical order starting from phase 6. for example, a 4-phase rail could consist of phases 6, 5, 4 and 3. for output 0, phases would be assigned starting from phase 0 in ascending sequential numerical order. automatic phase add and drop in order to produce the most optimal efficiency across a wide range of output loading, the modulator supports automatic dropping or adding of phases. use of automatic phase dropping is optional. if automatic phase dr opping is enabled, the number of active phases at any time is determined solely by load current. during operation, phases of output 1 will drop beginning with the lowest phase number assigned. phase dropping begins with the highest assigned phase number. figure 8 illustrates the typical characteristic of efficiency vs load current vs phase count. table 2. resistor values to address mapping r sa ( ) pmbus address r sa ( ) pmbus address 0 60h 1500 50h 180 61h 1800 51h 330 64h 2200 54h 470 65h 2700 55h 680 40h 3300 58h 820 41h 3900 59h 1000 44h 4700 5ch 1200 45h 5600 5dh load (a) figure 8. efficiency vs phase number efficiency (%) i1 i2 i3 i4 i5 0 20 60 80 100 120 140 160 180 40
isl68137 14 fn8757.0 september 27, 2016 submit document feedback phases are dropped one at a time with a user programmed drop delay between drop events. as an example, suppose the delay is set to 1ms and 3 phases are ac tive. should the load suddenly drop to a level needing only 1 phase, the isl68137 will begin by dropping a phase after 1ms. an additional phase will be dropped each 1ms thereafter until only 1 phase remains. in addition to the described load current add/drop thresholds, the fast phase add function provides a very rapid response to transient load conditions. this fe ature continuously monitors the system regulation error and should it exceed the user set threshold, all dropped phases will be readied for use. in this way, there is no delay should all phas es be needed to support a load transient. the fast phase add threshold is set in the powernavigator? gui. output current threshold for adding and dropping phases can also be configured. to ensure dropped phases have sufficient boot capacitor charge to turn on the high-side mosfet after a long period of disable, a boot refresh circuit turns on the low-side mosfet of each dropped phase to refresh the boot capacitor. frequency of the boot refresh is programmable via powernavigator?. output voltage configuration output voltage set points and thresholds for each output can be configured with powernavigator? gui. parameters such as output voltage, v out margin high/low and v out ov/uv fault thresholds can be configured wi th gui. additionally, output voltage and margin high/low can be adjusted during regulation via pmbus command vout_command, vout_margin_high and vout_margin_low for further tuning. the following v out relationships must be mainta ined for correct operation: vout_ov_fault_limit > vout_command (vout_margin_high and vout_margin_low, if used) > vout_uv_fault_limit. additionally, the v out commands are bounded by vout_max and vout_min to provide protection against incorrect set points being sent to the device. the isl68137 also incorporates avsb us functionality for high speed changes to the v out target. switching frequency switching frequency is user configurable over a range of 200khz to 1mhz. current sensing the isl68137 supports dcr, re sistor and smart power stage current sensing. connection to the various sense elements is accomplished via the cs and csrtn pins. current sensing inputs are high impedance differential inputs to reject noise and ground related inaccuracies. to accommodate a wide range of effective sense resistance, information about the effective sense resistance and required per phase current capability is utilized by the gui to properly configure the current sense circuitry. inductor dcr sensing dcr sensing takes advantage of the fact that an inductor winding has a resistive component (dcr) that will drop a voltage proportional to the inductor current. figure 9 shows that the dcr is treated as a lumped element with one terminal inaccessible for measurement. fortunately, a simple r-c network as shown in figure 10 is capable of reproducing the hidden dcr voltage. by simply matching the r-c time constant to the l/dcr time constant, it is possible to prec isely recreate the dcr voltage across the capacitor. this means that vdcr(t) = vc(t), thus preserving even the high frequency characteristic of the dcr voltage. modern inductors often have such low dcr values that the resulting signal is <10mv. to av oid noise problems, care must be taken in the pcb layout to proper ly place the r-c components and route the differential lines between controller and inductor. figure 9 graphically shows one pcb design method that places the r component near the induct or vphase and the c component very close to the ic pins. this minimizes routing of the noisy vphase and maximizes filtering near the ic. route the lines between the inductor and ic as a pair on a single layer directly to the controller. care must be take n to avoid routing the pair near any switching signals including phase, pwm etc. this is the method used by intersil on evaluation board designs. this method is sensing the resistance of a metal winding where the dcr value will increase with temperature. this must be compensated or the se nsed (and reported) current will increase with temperature. in order to compensate the temperature effect, the isl68137 provides temper ature sensing options and an internal methodology to apply the correction. resistive sensing for more accurate current sensing, a dedicated current sense resistor r sense in series with each output inductor can serve as the current sense element. this technique, however, reduces the overall converter efficiency due to the additional power loss on the current sense element r sense . figure 9. dcr sensing configuration csn csrtnn c r dcr l ? ? l dcr r c v out v phase ic current sense
isl68137 15 fn8757.0 september 27, 2016 submit document feedback a current sensing resistor has a distributed parasitic inductance, known as esl (equivalent series inductance, typically less than 4nh). consider the esl as a separate lumped quantity, as shown in figure 10 . the phase current i l , flowing through the inductor, will also pass through the esl. similar to dcr sensing described previously, a simple r-c network across the current sense resistor extracts the r sense voltage. simply match the esl/r sense time constant to the r-c time constant. figure 11 shows the sensed waveforms with and without matching rc when using resistive sense. pcb layout should be treated similar to that described for dcr sense. l/dcr or esl/r sen matching assuming the compensator design is correct, figure 12 shows the expected load transient response waveforms if l/dcr or esl/r sen is matching the r-c time constant. when the load current i out has a square change, the output voltage v out also has a square response, except for the potential overshoot at load release. however, there is always some uncertainty in the true parameter values involved in th e time constant matching and therefore, fine-tuning is generally required. if the r-c time constant is too large or too small, v c (t) will not accurately represent real-time i out (t) and will worsen the transient response. figure 13 shows the load transient response when the r-c timing constant is too small. in this condition, v out will sag excessively upon load in sertion and may create a system failure or early overcurrent trip. figure 14 shows the transient response when the r-c timing constant is too large. v out is sluggish in drooping to its final value. use these general guides if fine-tuning is needed. sps current sensing sps current sense is accomplished by sensing each sps imon output individually using vccs as a common reference. connect all sps iref input pins and all isl68137 csrtnn input pins together and tie them to vccs, then connect the sps imonn output pins to the corresponding isl68137 csn input pins. the signals should be run as differen tial pairs from the sps back to the isl68137. temperature sensing the isl68137 supports temperature sensing via bjt or smart power stage sense elements. support for bjt sense elements utilizes the well known delta vbe method and allows up to two sensors (mmbt3906 or similar) on each temperature sense input, tmon0 and tmon1. support for smart power stage utilizes a linear conversion algorithm and allows one sensor reading per pin. the conversion from voltage to temperature for smart power stage sensing is user programmable via the powernavigator? gui. sps temperature sensing measures the temperature dependent voltage output on the sps tmon pin. all of the sps devices attached to the output 0 rail have their tmon pins connected to the isl68137 tmon0 pin. all of the sps devices attached to the output 1 rail have their tmon pins connected to the isl68137 tmon1 pin. the reported temper ature is that of the highest temperature sps of the group. in addition to the external temperature sense, the ic senses its own die temperature, which may be monitored via powernavigator?. figure 10. sense resistor in series with inductor csn csrtnn c r rsense esl ? ? r sense r c v out v phase ic esl current sense figure 11. voltage across r with and without rc mismatched rc matched rc figure 12. desired load transient response waveforms i out v out figure 13. load transient response when r-c time constant is too small i out v out figure 14. load transient response when r-c time constant is too large i out v out
isl68137 16 fn8757.0 september 27, 2016 submit document feedback sensed temperature is utilized in the system for faults, telemetry and temperature compensation of sensed current. temperature compensation the isl68137 supports inductor dcr sensing, which generally requires temperature compensation due to the copper wire used to form inductors. copper has a positive temperature coefficient of approximately 0.39%/c. since the voltage across the inductor is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor dcr. compensating current sense for temperature variation generally requires that the current sensing element temperature and its temperature coefficient is known. while temperature coefficient is generally obtained easily, actual current sense element temperature is essentially impossible to measure directly. instead, a temperature sensor (a bjt for the isl68137) placed near the inductors is measured and the current sense element (dcr) temperature is calculat ed from that measurement. calculating current sense element temperature is equivalent to applying gain and offset correct ions to the temperature sensor measurement and the isl68137 supports both corrections. figure 15 depicts the block diagram of temperature compensation. a bjt placed near the inductors used for dcr sensing is monitored by the ic utilizing the well known delta vbe method of temperature sensing. t sense is the direct measured temperature of the bjt. because the bjt is not directly sensing dcr, corrections must be made such that t dcr reflects the true dcr temperature. corrections are applied according to the relationship shown in equation 1 , where k slope represents a gain scaling and t offset represents an offset correction. these parameters are provided by the designer via the powernavigator? gui: once t dcr has been determined, the compensated dcr value may be determined according to equation 2 , where dcr 25 is the dcr at +25c and t c is the temperature coefficient of copper (3900 ppm/c). t dcr = t actual here: thus, the temperature compensated dcr is now used to determine the actual value of current in the dcr sense element. in the physical pcb design, the temperature sense diode (bjt) is placed close to the inductor of the phase that is never dropped during automatic phase drop oper ation. additionally, a filter capacitor no larger than 500pf should be added near the ic between each tmon pin and vccs. this is shown in figure 16. lossless input current and power sensing input current telemetry is provided via an input current synthesizer. by utilizing the ic?s ability to precisely determine its operational conditions, input current can be synthesized to a high degree of accuracy without the need for a lossy sense resistor. fine-tuning of offset and gain are provided for in the gui. note that input current sense fine-tuning must be done after output current sense setup is finalized. with a precise knowledge of input current and voltage, input power may be computed. input current and power telemetr y is accessed via a pmbus and easily monitored in the powernavigator? gui. v in is monitored directly by the vinsen pin through a 1:5 resistor divider as shown in figure 17 . t dcr k slope t sense t offset + ? = (eq. 1) dcr corr dcr 25 1t c + t actual 25 C ?? ? ?? ? = (eq. 2) figure 15. block diagram of temperature compensation vbe vccs tmonx t offset t sense v out dcr current sense iphase# t c temperature compensation dcr corr to telemetry csx csrtnx k slope ic iphase# sw1 sw5 sw6 out1 l5 l6 l1 sw0 out0 tmon1 vccs ic tmon0 l0 optional auxiliary temperature sense optional auxiliary temperature sense figure 16. recommended placement of bjt
isl68137 17 fn8757.0 september 27, 2016 submit document feedback voltage regulation output voltage is sensed through the remote sense differential amplifier and digitized. from this point, the regulation loop is entirely digital. traditional pid co ntrols are utilized in conjunction with several enhanced methods to compensate the voltage regulation loop and tune the transient response. current feedback current feedback in a voltage regulator is often utilized to ease the stability design of the volt age feedback path. additionally, many microprocessors require the voltage regulator to have a controlled output resistance (known as load-line or droop regulation) and this is accompli shed utilizing current feedback. for applications requiring droop regulation, the designer simply specifies the output resi stance desired using the powernavigator? gui. current feedback stability benefits are available for rails that do not specify droop regulation such as system agent. for these applications, the designer may enable ac current feedback in the gui. with this configuration, the dc output voltage will be steady regardless of load current. power-on reset (por) initialization of the isl68137 begins after v cc crosses its rising por threshold. when por conditions are met, the internal 1.2v ldo is enabled and basic digital subsystem integrity checks begin. during this process, the co ntroller will load the selected user configuration from nvm as indicated by the config pin resistor value, read vin uvlo th resholds from memory and start the telemetry subsystem. with telemetry enabled, v in may be monitored to determine when it exceeds its user programmable rising uvlo threshold. once v cc and v in satisfy their respective voltage conditions, the co ntroller is in its shutdown state. it will transition to its active state and begin soft-start when the state of en0/en1 command a start-up. wh ile in shutdown mode, the pwm outputs are held in a high-i mpedance state to assure the drivers remain off. soft-start delay and ramp times it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for an output to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current management strategy or to precisely control how fast a load ic is turned on. the isl68137 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay and ramp-up/down times can be configured via powernavigator? gui. the device needs approximately 200s after enable to initialize before starting to ramp up. when the soft-start ramp period is set to 0ms, the output ramps up as quickly as the output load capacitance and loop settings allow. it is recommended to set the ramps to a non-zero value to prevent inadvertent fault conditions due to excessive inrush current. stored configuration selection as many as eight configurations may be stored an d used at any time using the on-board nonvolatile memory. configurations are assigned an identifier number between 0 and 7 at power-up. the device will load the configuration indicated by the 1% resistor value detected on the config pin. resistor values are used to indicate use of one of the ei ght possible configurations. table 3 provides the resistor value corresponding to each configuration identifier. only the most recent configuration with a given number can be loaded. the device supports a total of 8 stored operations. as an example, a configuration with th e identifier 0 could be saved 8 times or configurations with all 8 identifiers could be stored one time each for a total of 8 save operations. powernavigator? provides a simple interface to save and load configurations. fault monitoring and protection the isl68137 actively monitors te mperature, input voltage, output voltage and output current to detect and report fault conditions. fault monitors trigger configurable protective measures to prevent damage to a load. the power-good indicators, pg0/pg1, are provided for linking to external system monitors. a high level of flexibility is provided in the isl68137 fault logic. faults may be enabled or disabled individually. each fault type can also be configured to either latch off or retry indefinitely. figure 17. input voltage sense configuration adc vinsen ic 40.2k v in 10k 10nf ) config id 6800 0 1800 1 2200 2 2700 3 3300 4 3900 5 4700 6 5600 7
isl68137 18 fn8757.0 september 27, 2016 submit document feedback power-good signals the pg0/pg1 pins are open-dra in power-good outputs that indicate completion of the soft-start sequence and output voltage of the associated rail within the expected regulation range. the pg pins may be associated or disassociated with a number of the available fault types. this allows a system design to be tailored for virtually any condition. in addition, these power-good indicators will be pulled low when a fault (ocp or ovp) condition or uv condition is detected on the associated rail. output voltage protection output voltage is measured at the load sensing points differentially for regulation an d the same measurement is used for ovp and uvp. the fault th resholds are set using pmbus commands. figure 18 shows a simplified ovp/uvp block diagram. the output voltage comp arisons are done in the digital domain. the device responds to an output overvoltage condition by disabling the output, declaring a fault, setting the salrt pin, setting the pg pin and then puls ing the lfet until the output voltage has dropped below the threshold. similarly, the device responds to an output undervol tage condition by disabling the output, declaring a fault, setting the salrt pin and setting the pg pin. the output will not rest art until the en pin is cycled (unless the device is configured to retry). in addition, the isl68137 features open pin sensing protection to detect an open of the output voltage sensing circuit. when this condition is detected, contro ller operation is suspended. output current protection the isl68137 offers a comprehensive overcurrent protection scheme. each phase is protected from both excessive peak current and sustained current. in addition, the system is protected from sustained total output overcurrent. figure 19 depicts a block diagram of the system total output current protection scheme. in this scheme, the phase currents are summed to form isum. isum is then fed to dual response paths allowing the user to program separate lpf, threshold and response time. one path is inte nded to allow response more quickly than the other path. with this system, the user can allow high peak total current for a short time and a lower level of current for a sustained time. note that neither of these paths affect pwm activity on a cycle-by -cycle basis. the characteristics of each path are easily set in powernavigator?. in addition to total output current, the isl68137 provides an individual phase peak current lim it that will act on pwm in a cycle-by-cycle manner. this mean s that if a phase current is detected to exceed the oc threshold, the phase pwm signal will be inverted to move current away from the threshold. in addition to limiting positive or negative peak current on a cycle-by-cycle basis, individual phase oc can be configured to limit current indefinitely or to declare a faul t after a programmable number of consecutive oc cycles. this feature is useful for applications where a fault shutdown of the system would not be acceptable but some ability to limit ph ase currents is desired. figures 22 and 23 on page 19 depict this operatio n. if configured for indefinite current limit, the conver ter will act as a current source and v out will not remain at its regulation point. it should be noted that in this case, v out ov or uv protection action may occur, which could shut the regulator down. figure 18. ovp, uvp comparators rgndx vsenx adc isl68137 digital ov comparator threshold register + - digital uv comparator threshold register + - soc ph1 current synthesizer isum ? phn current synthesizer timer to fault block filter compare timer act filter fast sum oc limit delay timer to fault block filter compare timer act filter slow sum oc limit delay total output current fault switching period count to fault block compare count act +peak limit occount f sw clk -peak limit pulse by pulse limit may be set for indefinite limiting but no fault assertion switching period count to fault block compare count act uccount f sw clk pulse by pulse limit phase peak current limiting and fault iphasen negative peak limiting positive peak limiting may be set for indefinite limiting but no fault assertion figure 19. ocp functional diagram
isl68137 19 fn8757.0 september 27, 2016 submit document feedback an example of the ocp_fast and ocp_slow waveforms are shown in figures 20 and 21 . figure 20. ocp_fast placeholder pgood pwm ocp_slow_threshold ocp_fast_threshold ocp_fast counter filter time constant figure 21. ocp_slow placeholder pgood pwm ocp_fast_threshold ocp_slow_threshold ocp_slow counter filter time constant twarn pgood pwm positive_current_limiting_per_phase figure 22. positive peak phase current limiting figure 23. negative peak phase current limiting twarn pgood pwm negative_current_limiting_per_phase
isl68137 20 fn8757.0 september 27, 2016 submit document feedback smart power stage oc fault detect intersil smart power stage (sps) devices will output a large signal on their imon lines if peak current exceeds their preprogrammed threshold. (for more detail about this functionality, please refer to the relevant sps datasheet.) the isl68137 is equipped to detect this fault flag and immediately shut down. this detector is enabled on the gui overcurrent fault setup screen. this feature functions by detecting signals which exceed the current sense adc full-scale range. if this detector is disabled while using an intersil sps, the sps fault# signal must be connected to the controller enable pin of the associated rail. this will ensure that an sps oc event will be detected and the converter will shut down. thermal monitoring and protection the twarn pin indicates the temperature status of the voltage regulator. the twarn pin is an open-drain output and an external pull-up resistor is required. this signal is valid only after the controller is enabled. the twarn signal can be used to inform the system that the temperature of the voltage regulator is too high and the load should reduce its power consumption. twarn only indicates a thermal warning, not a fault. the thermal monitoring function block diagram is shown in figure 24 . the isl68137 has 2 over-temperature thresholds, which allow both warning and fault indications. each temperature sensor threshold can be independently programmed in the powernavigator? gui. figure 25 on page 20 shows the thermal warning to twarn and figure 26 on page 20 shows the over-temperature fault to shutdown. pgood and twarn can be configured to indicate these warning and fault thresholds via the powernavigator? gui. twarn vccs telemetry control tmax temp sensors temp monitor adc ic tmonx delta vbe figure 24. block diagram of thermal monitoring function figure 25. thermal warning to twarn low ot threshold high ot threshold pwm pgood twarn pwm pgood twarn high ot threshold low ot threshold figure 26. over-temperature fault
isl68137 21 fn8757.0 september 27, 2016 submit document feedback layout and design considerations in addition to tb379 , the following pcb layout and design strategies are intended to minimize the noise coupling, the impact of board parasitic impedances on converter performance and to optimize the heat dissipating capabilities of the printed circuit board. this section highli ghts some important practices, which should be followed during the layout process. table 4 provides general guidance on best practices related to pin noise sensitivity. use of good engineering judgment is required to implement designs based on criteria specific to the situation. table 4. pin design and/or layout consideration pin name noise sensitive description vinsen yes connects to the resistor divider between vin and gnd (see figure 17 on page 17 ). filter vinsen with 10nf to gnd. rgndx vsenx yes treat each of the remote voltage sense pairs as differential signals in the pcb layout. they should be routed side by side on the same layer. they should not be routed in proximity to noisy signals like pwm or phase. tie to ground when not used. pgx no open-drain. 3.3v maximum pull-up voltage. tie to ground when not used. scl, sda, salrt yes 50khz to 2mhz signal during communication, pair up with salrt and route carefully. 20 mils spacing within sda, salrt and scl; and more than 30 mils to all other signals. refer to the smbus design guidelines and place proper termination resistance for impedance matching. tie to ground when not used. avs_clk, avs_sda, avs_mda yes up to 50mhz signals during communication, route carefully. 20 mils spacing within clk, sda, mda; and more than 30 mils to all other signals. tie clk and mda to ground when not used. tmonx yes when diode sensing is utilized, vccs is the return path for the delta vbe currents. utilize a separate vccs route specifically for diode temp sense. a filter capacitor no greater than 500pf should be placed between each tmon pin and the vccs pin near the ic. tie to ground when not used. twarn no open-drain. 3.3v maximum pull-up voltage. vcc yes place at least 2.2f mlcc decoupling capacitor directly at the pin. vccs yes place 4.7f mlcc decoupling capacitor directly at the pin. pwm no avoid routing near noise sensitive analog lines such as current sense or voltage sense. csx csrtnx yes treat each of the current sense pairs as differential signals in the pcb layout. they should be routed side by side on the same layer. they should not be routed in proximity to noisy signals like pwm or phase. proper routing of current sense is perhaps the most critical of all the layout tasks. tie to ground when not used. gnd yes this epad is the return of pwm output drivers. use 4 or more vias to directly connect the epad to the power ground plane. general comments the layer next to the top or bottom layer is preferred to be ground layers, while the signal layers can be sandwiched in the ground layers if possible. table 4. pin design and/or layout consideration (continued) pin name noise sensitive description
isl68137 22 fn8757.0 september 27, 2016 submit document feedback pmbus operation the isl68137 pmbus slave address is pin selectable utilizing the sa pin and resistor value described in table 2 on page 13 . for proper operation, users should follow the pmbus protocol, as shown in ? pmbus protocol ? on page 23 . the supported pmbus addresses are in 8-bit format (i ncluding write and read bit): 80-8e, a0-ae, b0-be and c0-ce. the least significant bit of the 8-bit address is for write (0h) and read (1h). pmbus commands are in the range from 0x00h to 0xffh. for the isl68137, page 0 corresponds to output 0 and page 1 to output 1. for reference purposes, the 7-bit format addr esses are also summarized in table 5 . the pmbus data formats follow pmbus specification version 1.3 and smbus version 2.0. basic pmbus telemetry comm ands are summarized in ? pmbus command summary ? on page 24 . table 5. pmbus 8-bit and 7-bit format address (hex) 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 80/81 40 a0/a1 50 b0/b1 58 c0/c1 60 82/83 41 a2/a3 51 b2/b3 59 c2/c3 61 88/89 44 a8/a9 54 b8/b9 5c c8/c9 64 8a/8b 45 aa/ab 55 ba/bb 5d ca/cb 65 figure 27. simplified pmbus initialization timing diagram 1.2v vcc enable ~30ms vccs indefinitely pmbus command pmbus command pmbus command pmbus command v out program configuration (bt, tmax, ps, de, etc.) program configuration (bt, tmax, ps, de, etc.) use previous programmed configuration for start-up and operation vccs 3.3v por pll locked fac load config tel adc initialized start-up diagnostics done done customer config load program configuration (bt, tmax, ps, de, etc.)
isl68137 23 fn8757.0 september 27, 2016 submit document feedback pmbus protocol s slave address_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a 1 p s slave address_0 7 + 1 command code 1 8 a 1 a pec 8 1 a 1 p optional 9 bits for smbus/pmbus 1. send byte protocol 2. write byte/word protocol s slave address_0 1 7 + 1 command code 1 8 a 1 8 a 1 8 a 1 8 a 1 n 1 p 3. read byte/word protocol rs slave address_1 1 7 + 1 example command: 0 3h clear faults example command: 21h vout_command not used in i 2 c optional 9 bits for smbus/pmbus not used in i 2 c optional 9 bits for smbus/pmbus not used in i 2 c example command: 8b re ad_vout (two words, read voltage of the s elected rail). s: start condition a: acknowledge (0) n: not acknowledge (1) rs: repeated start condition p: stop condition pec: packet error checking r: read (1) w: write (0) 5. alert response address (ara, 0001_1001, 25h) for smbus and p mbus, not used for i 2 c s alert addr_1 1 7 + 1 1 7+1 a 1 a 8 1 a 1 p optional 9 bits for smbus/pmbus not used in i 2 c 1 a data byte pec 8 1 8 a 1 a 4. group command protocol - no m ore than one command can be sen t to the same address s slave addr2_0 1 7 + 1 1 a s slave addr1_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a low data byte high data byte pec 8 1 8 a 1 8 a 1 a 1 p rs slave addr3_0 1 7 + 1 optional 9 bits for smbus/pmbus 1 a not used in i 2 c not used for one byte word read not used for one byte word slave_address_1 pec low data byte high data byte pec command code 8 1 a command code 8 a (this will clear all of the bits in status byte for the selecte d rail) acknowledge or data from slave, isl68137 controller stop (p) bit is not allowed be fore the repeated start condition when reading contents of a register. a
isl68137 24 fn8757.0 september 27, 2016 submit document feedback pmbus command summary code command name description type data format default value default setting 00h page selects output 0, 1, or both r/w bit 00h page 0 01h operation enable/disable, margin settings r/w bit 08h off 02h on_off_config on/off configuration settings r/w bit 16h enable pin control 03h clear_faults clears all fault bits in all registers and releases the salrt pin write n/a n/a 10h write_protect write protection to sets of commands r/w bit 00h no write protection 20h vout_mode defines format for output voltage related commands read bit 40h direct format 21h vout_command sets the nominal v out target r/w direct 0384h 900mv 22h vout_trim applies trim voltage to v out set-point r/w direct 0000h 0mv 24h vout_max absolute maximum volt age setting r/w direct 08fch 2300mv 25h vout_margin_high sets v out target during margin high r/w direct 0640h 1600mv 26h vout_margin_low sets v out target during margin low r/w direct 00fah 250mv 27h vout_transition_rate slew rate setting for v out changes r/w direct 0064h 10mv/s 28h vout_droop sets the loadline (v/i slope) resistance for the output r/w direct 0000h 0v/a 2bh vout_min absolute minimum target voltage setting r/w direct 0000h 0mv 40h vout_ov_fault_limit sets the v out overvoltage fault threshold r/w direct 076ch 1900mv 44h vout_uv_fault_limit sets the v out undervoltage fault threshold r/w direct 0000h 0mv 4fh ot_fault_limit sets the over-temperatu re fault threshold r/w direct 007dh +125c 51h ot_warn_limit sets the over-temperatu re warning threshold r/w direct 07d0h +2000c 55h vin_ov_fault_limit sets the v in overvoltage fault threshold r/w direct 36b0h 14,000mv 59h vin_uv_fault_limit sets the v in undervoltage fault threshold r/w direct 1f40h 8,000mv 5bh iin_oc_fault_limit sets the i in overcurrent fault threshold r/w direct 0032h 50a 60h ton_delay sets the delay time from enable to v out rise r/w direct 0014h 200s 61h ton_rise turn-on rise time r/w direct 01f4h 500s 64h toff_delay turn-off delay time r/w direct 0000h 0s 65h toff_fall turn-off fall time r/w direct 01f4h 500s 78h status_byte first byte of status_word read bit n/a n/a 79h status_word summary of critical faults read bit n/a n/a 7ah status_vout reports v out faults read bit n/a n/a 7bh status_iout reports i out faults read bit n/a n/a 7ch status_input reports input faults read bit n/a n/a 7dh status_temperature reports temper ature warnings/faults read bit n/a n/a 7eh status_cml reports communication, memory, logic errors read bit n/a n/a 80h status_mfr_specific reports specific events read bit n/a n/a 88h read_vin reports input voltage measurement read direct n/a n/a 89h read_iin reports input current measurement read direct n/a n/a 8bh read_vout reports output voltage measurement read direct n/a n/a 8ch read_iout reports output current measurement read direct n/a n/a 8dh read_temperature_1 reports power stage temperature measurement read direct n/a n/a
isl68137 25 fn8757.0 september 27, 2016 submit document feedback pmbus use guidelines all commands can be read at any time always disable the outputs when writing comma nds that change device settings. exceptions to this rule are commands intended to be written while the device is enabled, for example, operation. pmbus data formats direct (d) the direct data format is a two byte two?s complement binary integer. bit field (bit) break down of bit field is provided in ? pmbus command detail ? on page 26 . 8eh read_temperature_2 reports tmon0 te mperature measurement read direct n/a n/a 8fh read_temperature_3 reports tmon1 te mperature measurement read direct n/a n/a 96h read_pout reports output power read direct n/a n/a 97h read_pin reports input power read direct n/a n/a 98h pmbus_revision reports specific events read bit 33h revision 1.3 adh ic_device_id reports devi ce identification information read bit 49d22700h isl68137 aeh ic_device_rev report s device revision information read bit n/a n/a e7h apply_settings instructs device to ap ply pmbus setting changes write bit 01h n/a f2h restore_config allows selection of co nfigurations from nvm write bit n/a n/a pmbus command summary (continued) code command name description type data format default value default setting
isl68137 26 fn8757.0 september 27, 2016 submit document feedback pmbus command detail page (00h) definition: selects controller 0, controller 1 or both controllers 0 and 1 to receive commands. all comm ands following this command will be received and acted on by th e selected controller or controllers. data length in bytes: 1 data format: bit field type: r/w default value: 00h operation (01h) definition: sets enable state when configured for pmbu s enable. sets the source of the target v out . the device always acts on faults during margin. the table below reflects the valid settings for the device. paged or global: paged data length in bytes : 1 data forma t: bit field type : r/w default value : 08h command page (00h) format bit field bit position 76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value 00000000 bits 7:4 bits 3:0 page 0000 0000 0 0000 0001 1 1111 1111 both command operation (01h) format bit field bit position 76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value 00001000 bit number purpose bit value meaning bits 7:6 enable/disable 00 immediate off (decay) 01 soft-off (use toff_delay and toff_fall) 10 on bits 5:4 vout source 00 vout_command 01 vout_margin_low 10 vout_margin_high 11 avsbus target rail voltage bits 3:2 margin response 10 act on faults bit 1 avsbus copy 0 vout_command remains unchanged 1 avsbus target rail voltage changes are copied to vout_command bit 0 not used 0 not used
isl68137 27 fn8757.0 september 27, 2016 submit document feedback on_off_config (02h) definition: configures the interpretation of the operation command an d the enable pin (en). the below table reflects the valid settings for the device. paged or global: global data length in bytes: 1 data format: bit field type: r/w default value: 16h (enable pin control) clear_faults (03h) definition: clears all fault bits in all registers and releases the salrt pin (if asserted) simultaneously. if a fault condition still exit s, the bit will reassert immediately. this command will not restart a device if it is shut down, it will only clear the faults. paged or global: global data length in bytes: 0 data format: n/a type: write only default value: n/a command on_off_config (02h) format bit field bit position 76543210 access r/w r/w r/w r/w r/w r/w r/w r/w function see following table default value 00000000 bit number purpose bit value meaning 7:5 not used 000 not used 4:2 sets the source of enable 000 device always enabled regardless of pin or operation command state 101 device starts from enable pin only 110 device starts from operation command only 111 device starts from operat ion command and enable pin 1 enable pin polarity 1 active high only 0 enable pin turn off action 1 turn off immediately with decay 0 use programmed toff_delay and toff_fall settings
isl68137 28 fn8757.0 september 27, 2016 submit document feedback write_protect (10h) definition: sets the write protection of certain configuration commands. paged or global: global data length in bytes: 1 data format: bit field type: r/w default value: 00h (enable all writes) vout_mode (20h) definition: returns the supported v out mode. this device only supports absolute direct mode. paged or global: global data length in bytes: 1 data format: bit field type: read only default value: 40h units: n/a equation: n/a vout_command (21h) definition: sets the value of v out when the operation command is conf igured for pmbus nominal operation. paged or global: paged data length in bytes: 2 data format: direct type: r/w default value: 0384h (900mv) units: mv equation: vout_command = (direct value) range : vout_min to vout_max command write_protect (10h) format bit field bit position 7 6 5 4 3:0 2 1 0 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value 00000000 settings protection 40h disables all writes except to write_protect, operation, clear_faults, page 20h disables all writes except all above plus on_off_config and v out_command, vout_trim 00h enables all writes note: any settings other than the 3 shown in th e table will result in an invalid data fault. command vout_command (21h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000001110000100
isl68137 29 fn8757.0 september 27, 2016 submit document feedback vout_trim (22h) definition: sets a fixed trim voltage to the output voltage command value. this command is typically used to calibrate a device in the application circuit. paged or global: paged data length in bytes: 2 data format: direct type: r/w default value: 0000h (0mv) units: mv equation: vout_trim = (direct value) range : 250mv vout_max (24h) definition: sets the maximum allowed v out target regardless of any other commands or combinations. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 08fch (2300mv) units: mv equation: vout_max = (direct value) range : 0mv to 3300mv command vout_trim (22h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000000000000 command vout_max (24h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000100011111100
isl68137 30 fn8757.0 september 27, 2016 submit document feedback vout_margin_high (25h) definition: sets the value of v out when the operation command is configured for margin high. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0640h (1600mv) units: mv equation: vout_margin_high = (direct value) range : vout_min to vout_max vout_margin_low (26h) definition: sets the value of v out when the operation command is configured for margin low. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 00fah (250mv) units: mv equation: vout_margin_low = (direct value) range : vout_min to vout_max command vout_margin_high (25h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000011001000000 command vout_margin_low (26h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000011111010
isl68137 31 fn8757.0 september 27, 2016 submit document feedback vout_transition_rate (27h) definition: sets the output voltage rate of change during regulation. changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0064h (10mv/s) units: v/s equation: vout_transition_rate = (direct value)*100 range : 100v/s to 100mv/s vout_droop (28h) definition: sets the output voltage rate of change during regulation. changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0000h (0v/a) units: v/a equation: vout_droop = (direct value)*10 range : 0v/a to 16,000v/a command vout_transition_rate (27h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000001100100 command vout_droop (28h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000000000000
isl68137 32 fn8757.0 september 27, 2016 submit document feedback vout_min (2bh ) definition: sets the minimum allowed v out target regardless of any other commands or combinations. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0000h (0mv) units: mv equation: vout_min = (direct value) range : 0v to vout_max vout_ov_fault_limit (40h ) definition: sets the output overvoltage fault threshold. changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 076ch (1900mv) units: mv equation: vout_ov_fault_limit = (direct value) range : 0v to vout_max command vout_min (2bh) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000000000000 command vout_ov_fault_limit (40h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000011101101100
isl68137 33 fn8757.0 september 27, 2016 submit document feedback vout_uv_fault_limit (44h ) definition: sets the v out undervoltage fault threshold. this fault is masked during ramp or when disabled. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0000h (0mv) units: mv equation: vout_uv_fault_limit = (direct value) range : 0v to vout_max ot_fault_limit (4fh) definition: sets the power stage over -temperature fault limit. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 007dh (+125c) units: c equation: ot_fault_limit = (direct value) range : 0c to +2000c command vout_uv_fault_limit (44h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000000000000 command ot_fault_limit (4fh) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000001111101
isl68137 34 fn8757.0 september 27, 2016 submit document feedback ot_warn_limit (51h) definition: sets the system over-temperature warn limit. if any measured temperature exceeds this value, the device will: ? set the temperature bit in status_byte and status_word ? set the ot_warning bit in status_temperature ? set the salrt pin ?set the twarn pin paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 07d0h (+2000c) units: c equation: ot_warn_limit = (direct value) range : 0 to +2000c vin_ov_fault_limit (55h) definition: sets the v in overvoltage fault threshold. changes to this setting re quire a write to the apply_settings command before the change will take effect. paged or global: global data length in bytes: 2 data format: direct type: r/w default value: 36b0h (14,000mv) units: mv equation: vin_ov_fault_limit = (direct value) range : 0mv to 16,000mv command ot_warn_limit (51h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000011111010000 command vin_ov_fault_limit (55h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0011011010110000
isl68137 35 fn8757.0 september 27, 2016 submit document feedback vin_uv_fault_limit (59h) definition: sets the v in undervoltage fault threshold. also referred to as unde rvoltage lockout (uvlo). changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: global data length in bytes: 2 data format: direct type: r/w default value: 1f40h (8,000mv) units: mv equation: vin_uv_fault_limit = (direct value) range : 0mv to 16,000mv iin_oc_fault_limit (5bh) definition: sets the i in overcurrent fault threshold. changes to this setting require a write to the apply_settings command before the change will take effect. paged or global: global data length in bytes: 2 data format: direct type: r/w default value: 0032h (50a) units: a equation: iin_oc_fault_limit = (direct value) range : 0a to 50a command vin_uv_fault_limit (59h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0001111101000000 command iin_oc_fault_limit (5bh) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000000110010
isl68137 36 fn8757.0 september 27, 2016 submit document feedback ton_delay (60h) definition: sets the delay time of v out during enable. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0014h (200s) units: s equation: ton_delay = (direct value)*10 range : 200s to 655,340s ton_rise (61h) definition: sets the rise time of v out during enable. changes to this setting require a write to the apply_settings command before the change will take effect. this function uses the value of v out to calculate rise time, so apply_ settings must be sent after any change to the v out target for accurate rise time. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 01f4h (500s) units: s equation: ton_rise = (direct value) range : 0s to 10,000s command ton_delay (60h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000000010100 command ton_rise (61h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000111110100
isl68137 37 fn8757.0 september 27, 2016 submit document feedback toff_delay (64h) definition: sets the delay time of v out during disable. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 0000h (0s) units: s equation: toff_delay = (direct value)*10 range : 0s to 10,000s toff_fall (65h) definition: sets the fall time of v out during disable. changes to this setting requir e a write to the apply_settings command before the change will take effect. this function uses the value of v out to calculate fall time, so apply_settings must be sent after any change to the v out target for accurate fall time. paged or global: paged data length in bytes: 2 data format: direct type : r/w default value: 01f4h (500s) units: s equation: toff_fall = (direct value) *1 range : 0s to 10,000s command toff_delay (64h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000000000000 command toff_fall (65h) format direct bit position 1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer default value 0000000111110100
isl68137 38 fn8757.0 september 27, 2016 submit document feedback status_byte (78h) definition: returns a summary of the unit?s fault status. based on the info rmation in this byte, the host can get more information by reading the appropriate status registers. a fault in either output will be reported here. paged or global: global data length in bytes: 2 data format: bit field type : read only default value: n/a command status_byte (78h) format bit field bit position 76543210 access rrrrrrrr function see following table bit number status bit name meaning 7not used not used 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0 none of the above a status change other than those listed above has occurred.
isl68137 39 fn8757.0 september 27, 2016 submit document feedback status_word (79h) definition: returns a summary of the device?s fault status. based on the in formation in these bytes, the host can get more information by reading the appropriate status registers. a fault in either output will be re ported here. the low byte of the status_word co ntains the same information as the status_byte (78h) command. paged or global: global data length in bytes: 2 data format: bit field type : read only default value: n/a command status_word (79h) format bit field bit position 1514131211109876543210 access rrrrrrrrrrrrrrrr function see following table bit number status bit name meaning 15 v out an output voltage fault has occurred. 14 iout an output current fault has occurred. 13 input an input voltage fault has occurred. 12 mfr_specific a manufacturer specific event has occurred. 11 power_good # the power_good signal, if present, is negated. ( note 8 ) 10:7 not used not used 6 off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 vout_ov_fault an output overvoltage fault has occurred. 4 iout_oc_fault an output overcurrent fault has occurred. 3 vin_uv_fault an input undervoltage fault has occurred. 2 temperature a temperature fault or warning has occurred. 1 cml a communications, memory or logic fault has occurred. 0 none of the above a status change other than those listed above has occurred. note: 8. if the power_good# bit is set, this indicates that the power_g ood signal, if present, is signal ing that the output power is n ot good.
isl68137 40 fn8757.0 september 27, 2016 submit document feedback status_vout (7ah) definition: returns a summary of output voltage faults. paged or global: paged data length in bytes: 1 data format: bit field type : read only default value: n/a status_iout (7bh) definition: returns a summary of output current faults. paged or global: paged data length in bytes: 1 data format: bit field type : read only default value: n/a command status_vout (7ah) format bit field bit position 76543210 access rrrrrrrr function see following table bit number status bit name meaning 7 vout_ov_fault indicates an output overvoltage fault. 6:5 not used not used 4 vout_uv_fault indicates an output undervoltage fault. 3 vout_max warning indicates an output voltage maximum warning. 2:0 not used not used command status_iout (7bh) format bit field bit position 76543210 access rrrrrrrr function see following table bit number meaning 7 an output overcurrent fault has occurred. 6 an output overcurrent and undervoltage fault has occurred. 5:4 not used 3 a current share fault has occurred. 2:0 not used
isl68137 41 fn8757.0 september 27, 2016 submit document feedback status_input (7ch) definition: returns a summary of input voltage faults. paged or global: global data length in bytes: 1 data format: bit field type : read only default value: n/a status_temperature (7dh) definition: returns a summary of temperature related faults. paged or global: global data length in bytes: 1 data format: bit field type : read only default value: n/a command status_input (7ch) format bit field bit position 76543210 access rrrrrrrr function see following table bit number meaning 7 an input overvoltage fault has occurred. 6:5 not used 4 an input undervoltage fault has occurred. 3not used 2 an input overcurrent fault has occurred. 1:0 not used command status_temperature (7dh) format bit field bit position 76543210 access rrrrrrrr function see following table bit number meaning 7 an over-temperature fault has occurred. 6 an over-temperature warning has occurred. 5not used 4 an under-temperature fault has occurred 3:0 not used
isl68137 42 fn8757.0 september 27, 2016 submit document feedback status_cml (7eh) definition: returns a summary of any communicat ions, logic and/or memory errors. paged or global: global data length in bytes: 1 data format: bit field type : read only default value: n/a status_mfr_specific (80h) definition: returns the status of specific information detailed below. paged or global: global data length in bytes: 1 data format: bit field type: read only default value: n/a command status_cml (7eh) format bit field bit position 76543210 access rrrrrrrr function see following table bit number meaning 7 invalid or unsupported pmbus command was received. 6 the pmbus command was sent with invalid or unsupported data. 5 a packet error was detected in the pmbus command. 4 memory fault detected. 3 processor fault detected. 2not used 1 a pmbus command tried to write to a read-only or protected co mmand, or a communication fault other than the ones listed in this table has occurred. 0 a memory or logic fault not listed above was detected. command status_mfr_specific (80h) format bit field bit position 76543210 access rrrrrrrr function see following table bit meaning 7:2 not used 1 otp nvm memory is full 0not used
isl68137 43 fn8757.0 september 27, 2016 submit document feedback read_vin (88h) definition: returns the input voltage reading. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: mv equation: read_vin = (direct value) read_iin (89h) definition: returns the input current reading. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: a equation: read_iin = (direct value)/100 read_vout (8bh) definition: returns the output voltage reading. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: mv equation: read_vout = (direct value) command read_vin (88h) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_iin (89h) format direct bit position 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access rrrrrrrrrrrrrrrr function two?s complement integer command read_vout (8bh) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer
isl68137 44 fn8757.0 september 27, 2016 submit document feedback read_iout (8ch) definition: returns the output current reading. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: a equation: read_iout = (direct value)/10 read_temperature_1 (8dh) definition: returns the temperature reading of the power stage. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: c equation: read_temperature_1 = (direct value) read_temperature_2 (8eh) definition: returns the temperature reading from a remote diode connected to tmon0 when configured for diode sensing. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: c equation: read_temperature_2 = (direct value) command read_iout (8ch) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_temperature_1 (8dh) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_temperature_2 (8eh) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer
isl68137 45 fn8757.0 september 27, 2016 submit document feedback read_temperature_3 (8fh) definition: returns the temperature reading from a remote diode connected to tmon1 when configured for diode sensing. paged or global: global data length in bytes: 2 data format: direct type: read only default value: n/a units: c equation: read_temperature_3 = (direct value) read_pout (96h) definition: returns the output power. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: w equation: read_pout = (direct value) read_pin (97h) definition: returns the input power. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: w equation: read_pin = (direct value) command read_temperature_3 (8fh) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_pout (96h) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command read_pin (97h) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer
isl68137 46 fn8757.0 september 27, 2016 submit document feedback pmbus_revision (98h) definition: returns the revision of the pmbus specific ation to which the device is compliant. data length in bytes: 1 data format: bit field type: read only default value: 33h (part 1 revision 1.3, part 2 revision 1.3) ic_device_id (adh) definition: returns device identification information. paged or global: global data length in bytes: 4 data format: bit field type: block read default value: 49d22700h ic_device_rev (aeh) definition: returns device revision information. paged or global: global data length in bytes: 4 data format: bit field type: block read default value: n/a command pmbus_revision (98h) format bit field bit position 76543210 access rrrrrrrr function see following table default value 00110011 bits 7:4 part 1 revision bits 3:0 part 2 revision 0000 1.0 0000 1.0 0001 1.1 0001 1.1 00101.200101.2 0011 1.3 0011 1.3 command ic_device_id (adh) format block read byte position 3210 function mfr code id high byte id low byte reserved default value 49h d2h 27h 00h command ic_device_rev (aeh) format block read bit position 23:16 15:8 7:4 3:0 function firmware revision factory configuration chip foundry site ic revision default value n/a n/a n/a n/a
isl68137 47 fn8757.0 september 27, 2016 submit document feedback apply_settings (e7h) definition: instructs the controller to utilize new pmbus parameters. send 01h to this command after making one or more changes to certain pmbus threshold commands that require rescaling of operational values. the commands that require this are vout_transition_rate, vout_droop, vout_ov_fault_limit, vi n_ov_fault_limit, vin_uv_fault_limit, iin_oc_fault_limit, ton_rise, and toff_fall. paged or global: global data length in bytes: 2 data format: bit type: write only default value: 01h units: n/a equation: n/a restore_config (f2h) definition: identifies the configuration to be restored from nvm and loads the store?s settings into the device?s active memory. paged or global: global data length in bytes: 1 data format: bit type: write only default value: n/a command restore_config (f2h) format bit field bit position 76543210 access r/wr/wr/wr/wr/wr/wr/wr/w function see following table default value n/a n/a n/a n/a n/a n/a n/a n/a bit number status bit name meaning 7:4 reserved reserved 3:0 config selected configuration to restore
isl68137 48 fn8757.0 september 27, 2016 submit document feedback adaptive voltage scaling (avsbu s) functionality and operation the avsbus interface provides a high speed (up to 50mhz) serial interface to the isl68137, allowing implementation of advanced voltage scaling functions that support increased system efficiency and performance. devices equipped with avsbus master capabil ity may use the interface to enable rapid supply voltage changes to support low power consumption modes as well as high performance modes. due to the advanced digital regulation loop employed, the isl68137 is well equipped to support very rapid transition rat es. all commands are readable at al l times, but they cannot be written unle ss the device is set to avsbus control. avsbus master send subframe function start code r/w command type command code rail select command data crc size (bits) 22 1 4 4 16 3 setting 01b 00b = write data and commit 11b = read data 0b = avsbus data 0h = target rail voltage 1h = transition rate 2h = rail current 3h = temperature 4h = voltage reset eh = avsbus status fh = avsbus version 0h = rail 0 1h = rail 1 fh = broadcast read = ffh write = see ? avsbus command detail ? on page 49 avsbus slave response subframe function slave ack 0b status response command data not used crc size (bits) 215 1653 setting 00b = command acknowledged, action taken 01b = command acknowledged, no action 10b = bad crc, no action 11b = invalid requ est, no action 0b bit 5 = vdone. sets to 1 when v out target is reached bit 4 = status alert. sets to 1 if a bit in avsbus status register (excluding from vdone) has set bit 3 = avsbus control. sets to 1 when avsbus control is enabled bits 2:0 = not used write = ffh read = see ? avsbus command detail ? on page 49 not used 11111b
isl68137 49 fn8757.0 september 27, 2016 submit document feedback avsbus command detail target rail voltage (0h) definition: sets or reads the target rail voltage set point. 1mv per lsb. the initial set point is copied from the pmbus command vout_command when avsbus operation is selected. paged or global: paged data length in bytes: 2 data format: direct type: r/w default value: value of pmbus vout_command units: mv equation: target rail voltage = (direct value) range: limited to the pmbus command values of vout_min and vout_max transition rate (1h) definition: sets or reads the rise and fall transition rates. 1mv/s pe r lsb. the initial value matche s pmbus transition rates until updated through avsbus. paged or global: paged data length in bytes: 2 data format: direct type: r/w default value: value of pmbus vout_transition_rate for rise and fall units: mv/s equation: transition rate = (direct value) command target rail voltage (0h) format direct bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function two?s complement integer command transition rate (1h) format direct bit position1514131211109876543210 access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function rise transition rate, two?s complement inte ger fall transition rate, two?s complement integer default value n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a
isl68137 50 fn8757.0 september 27, 2016 submit document feedback rail current (2h) definition: returns the output current reading. 10ma per lsb. a filter is applied to this reading, and it is configurable in powernavigator?. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: a equation: rail current= (direct value)/100 temperature (3h) definition: returns the power stage temperature reading. 0.1c per lsb. this value is copied from the read_temperature_1 pmbus command. paged or global: paged data length in bytes: 2 data format: direct type: read only default value: n/a units: c equation: temperature = (direct value)/10 voltage reset (4h) definition: sets target rail voltage to match that of the vout_command pmbus command. paged or global: paged data length in bytes: 2 data format: bit field type: write only default value: 00h units: n/a command rail current (2h) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command temperature (3h) format direct bit position1514131211109876543210 access rrrrrrrrrrrrrrrr function two?s complement integer command voltage reset (4h) format bit field bit position1514131211109876543210 access wwwwwwwwwwwwwwww function send all 0?s default value0000000000000000
isl68137 51 fn8757.0 september 27, 2016 submit document feedback avsbus status (eh) definition: returns the device status. vdone indicates that the v out setting target has been reached. ot warn indicates that one or more of the device?s temperature measurements has exceeded the over-temperature warning threshold set by the ot_warn_limit pmbus command. the device sets the avs_sda line low to noti fy the host any time a bit in this register has been set. paged or global: paged data length in bytes: 2 data format: bit field type: read only default value: n/a units: n/a avsbus version (fh) definition: returns the version of the avsbus specification to which the device is compliant. this device complies with version 1.3. paged or global: global data length in bytes: 2 data format: bit field type: read only default value: 00h units: n/a command avsbus status (eh) format bit field bit position 15 14 13 12 11:0 accessrrrrr function vdone not used not used ot warn not used default value n/a 0 0 n/a 0
isl68137 52 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8757.0 september 27, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback c about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go to web to make sure you have the latest revision. date revision change september 27, 2016 fn8757.0 initial release
isl68137 53 fn8757.0 september 27, 2016 submit document feedback package outline drawing l48.6x6b 48 lead quad flat no-lead plastic package rev 0, 9/09 typical recommended land pattern detail "x" side view top view bottom view located within the zone indica ted. the pin #1 i dentifier may be unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifie r is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metalli zed terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6.00 a b pin 1 index area (4x) 0.15 6 6.00 4.4 37 44x 0.40 4x pin #1 index area 48 6 4 .40 0.15 1 ab 48x 0.45 0.10 24 13 48x 0.20 4 0.10 c m 36 25 12 max 1.00 seating plane base plane 5 c 0 . 2 ref 0 . 00 min. 0 . 05 max. 0.10 c 0.08 c c see detail "x" ( 5. 75 typ ) ( 4. 40 ) ( 48x 0 . 20 ) ( 48x 0 . 65 ) ( 44 x 0 . 40 ) 0.05 m c for the most recent package outline drawing, see l48.6x6b .

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